1. Field of the Invention
The present invention relates generally to variable gain amplifiers and particularly to linear gain amplifiers.
2. Description of the Background Art
FIG. 5 shows a variable gain amplifier configured of an amplification circuit 100 and a control circuit 400 controlling a gain of amplification circuit 100. Amplification circuit 100 is configured, as described hereinafter. Amplification circuit 100 includes n-channel MOS transistors M1-M6 (first to sixth MOS transistors, respectively), and load resistances Z1 and Z2 (first and second load resistances, respectively). Herein, transistors M1 and M2 are identical in characteristics, and so are transistors M3 and M4, and transistors M5 and M6. Herein, xe2x80x9cidentical in characteristicsxe2x80x9d means xe2x80x9cequal in threshold voltage, gain constant, transconductance provided when a uniform current flows, and in drain resistance.xe2x80x9d
Transistors M3 and M5 have their respective drains connected together at a point connected to a first output terminal. Transistors M4 and M6 have their respective drains connected together at a point connected to a second output terminal. Transistors M3 and M4 have their respective sources connected together at a point connected to transistor M2 at the drain.
Transistors M5 and M6 have their respective sources connected together at a point connected to transistor M1 at the drain.
Transistor M1 is provided with a gate terminal Vc1 connected to control circuit 400 and has its source connected to a first fixed potential (a ground potential). Transistor M2 is provided with a gate terminal Vc2 connected to control circuit 400 and has its source connected to the first fixed potential (the ground potential).
Transistor M3 has its gate connected to its drain. Transistor M4 has its gate connected to its drain. Transistor M6 has its gate connected to a first input terminal IN1. Transistor M5 has its gate connected to a second input terminal IN2.
Resistance Z1 has one end connected to a second fixed potential Vdd and the other end to a first output terminal OUT1. Resistance Z2 has one end connected to the second fixed potential Vdd and the other end to a second output terminal OUT2.
Input terminals IN1 and IN2 have potentials Vinxe2x88x92 and Vin+, respectively, and output terminals OUT1 and OUT2 have potentials Vout+ and Voutxe2x88x92, respectively, and transistors M1 and M2 pass currents I1 and I2, respectively, for the sake of illustration.
FIG. 6 shows a circuit equivalent to the amplification circuit. In the figure, gm1 represents transconductance of transistors M5 and M6, gm2 represents transconductance of transistors M3 and M4, rd1 represents drain resistance of transistors M5 and M6, rd2 represents drain resistance of transistors M3 and M4, and Z represents resistance of load resistances Z1 and Z2. From this figure, the amplification circuit has a gain gain, as represented by the following equation:                               gain          =                                    "LeftBracketingBar"                              (                                                      (                                                                  Vout                        +                                            -                                              Vout                        -                                                              )                                                        (                                                                  Vin                        +                                            -                                              Vin                        -                                                              )                                                  )                            "RightBracketingBar"                        ⁢                          
                        ⁢                          xe2x80x83                        =                          g              ⁢                              xe2x80x83                            ⁢              m              ⁢                              xe2x80x83                            ⁢                              1                ·                                  (                                                                                                              rd                          ⁢                                                      xe2x80x83                                                    ⁢                          1                                                //                                                  rd                          ⁢                                                      xe2x80x83                                                    ⁢                          2                                                                    //                                              1                                                  gm                          ⁢                                                      xe2x80x83                                                    ⁢                          2                                                                                      //                    Z                                    )                                                                    ,                            (        A1        )            
wherein // indicates an operation performed to calculate combined resistance of parallel connection. If rd1, rd2 greater than  greater than 1/gm2, Z then gain is approximated, as follows:                               gain          ≅                      gm            ⁢                          xe2x80x83                        ⁢                          1              ·                              (                                                      1                                          gm                      ⁢                                              xe2x80x83                                            ⁢                      2                                                        //                  Z                                )                                                    ⁢                  
                ⁢                  xe2x80x83                =                              gm            ⁢                          xe2x80x83                        ⁢                          1              ·                              (                                                      Z                                          gm                      ⁢                                              xe2x80x83                                            ⁢                      2                                                                            Z                    +                                          1                                              gm                        ⁢                                                  xe2x80x83                                                ⁢                        2                                                                                            )                                              ⁢                      
                    ⁢                      xe2x80x83                    =                                                    gm                ⁢                                  xe2x80x83                                ⁢                1                                            gm                ⁢                                  xe2x80x83                                ⁢                2                                      ·                                          1                                                      1                                                                  Z                        ·                        gm                                            ⁢                                              xe2x80x83                                            ⁢                      2                                                        +                  1                                            .                                                          (        A2        )            
If xcexcn represents an average surface mobility, Cox represents a gate capacitance per unit area, (W/L)1 represents a channel width/a channel length of transistors M5 and M6, and (W/L)2 represents a channel width/a channel length of transistors M3 and M4, then gm1 and gm2 are represented by the following equations:                               gm          ⁢                      xe2x80x83                    ⁢          1                =                                                                              UnCox                  ⁡                                      (                                          W                      L                                        )                                                  1                            ·              I                        ⁢                          xe2x80x83                        ⁢            1                                              (        A3        )                                          gm          ⁢                      xe2x80x83                    ⁢          2                =                                                                                                  UnCox                    ⁡                                          (                                              W                        L                                            )                                                        2                                ·                I                            ⁢                              xe2x80x83                            ⁢              2                                .                                    (        A4        )            
By substituting expressions A3 and A4 into expression A2, the following expression:                     gain        ≅                                                                                                                        UnCox                      ⁡                                              (                                                  W                          L                                                )                                                              1                                    ·                  I                                ⁢                                  xe2x80x83                                ⁢                1                                                                                                                                UnCox                      ⁡                                              (                                                  W                          L                                                )                                                              2                                    ·                  I                                ⁢                                  xe2x80x83                                ⁢                2                                              xc3x97                      1                          1                              Z                ⁢                                                                                                                              UnCox                          ⁡                                                      (                                                          W                              L                                                        )                                                                          2                                            ·                      I                                        ⁢                                          xe2x80x83                                        ⁢                    2                                                                                                          (        A5        )            
is obtained.
From expression A5, if Z is sufficiently large, then an expression:
gain xe2x88x9d(I1/I2)0.5 xe2x80x83xe2x80x83(A6) 
is provided and gain is proportional to a square root of a ratio of current I1 to current I2.
Control circuit 400 is configured, as described hereinafter. Control circuit 400 includes p-channel MOS transistors M21 and M22, n-channel MOS transistors M11 and M12, and a constant current source Ibias1. Herein, transistors M11 and M12 are identical in characteristics, and so are transistors M21 and M22.
Constant current source Ibias1 outputs a constant current Ibs1.
Transistors M21 has its source connected to constant current source Ibias1, its drain connected to transistor M11 at the drain, and its gate receiving a control voltage Vcon1.
Transistor M22 has its source connected to constant current source Ibias1, its drain connected to transistor M12 at the drain, and its gate receiving a control voltage Vcon2.
Transistor M11 has its source connected to a first fixed potential (a ground potential), its drain connected to its gate and transistor M21 at the drain, and gate terminal Vc1 connected to gate terminal Vc1 of transistor M1 of amplification circuit 100.
Transistor M12 has its source connected to the first fixed potential (the ground potential), its drain to its gate and transistor M22 at the drain, and gate terminal Vc2 to gate terminal Vc2 of transistor M2 of amplification circuit 100.
Constant current source Ibias1 has one end connected to a second fixed potential Vdd and the other end to transistors M21 and M22 at their respective sources.
Control circuit 400 operates, as described hereinafter. Transistors M21 and M22 are provided with a gain constant K and a threshold voltage Vth for the sake of illustration. Transistors M21 and M22 pass currents Id1 and Id2, respectively, and their respective gate-source voltages are represented as Vgs1 and Vgs2, respectively, for the sake of illustration. Currents Id1 and Id2 are represented by the following equations:
Ibs1=Id1+Id2 xe2x80x83xe2x80x83(A7) 
Id1=Kxc3x97(Vgs1xe2x88x92Vth)2 xe2x80x83xe2x80x83(A8) 
Id2=Kxc3x97(Vgs2xe2x88x92Vth)2 xe2x80x83xe2x80x83(A9). 
Herein, if a point S has a potential Vs then the following equations:
Vgs1=Vcon1xe2x88x92Vs xe2x80x83xe2x80x83(A10) 
Vgs2=Vcon2xe2x88x92Vs xe2x80x83xe2x80x83(A11) 
are established.
Herein, if
Vcon=Vcon2xe2x88x92Vcon1 xe2x80x83xe2x80x83(A12) 
then from expressions A7-A12 the following expressions:
{square root over (K)} Vcon={square root over (Ibs1xe2x88x92Id1)}xe2x88x92{square root over (Id1)}xe2x80x83xe2x80x83(A13) 
={square root over (Id2)}xe2x88x92Ibs1xe2x88x92{square root over (Id2)}xe2x80x83xe2x80x83(A14) 
are obtained.
Expressions A13 and A14 are transformed to obtain the following two expressions:                               Id          ⁢                      xe2x80x83                    ⁢          1                =                              1            2                    ⁡                      [                                          Ibs                ⁢                                  xe2x80x83                                ⁢                1                            +                                                                                          2                      ⁢                      Ibs                      ⁢                                              xe2x80x83                                            ⁢                                              1                        ·                        K                                                              -                                                                  (                                                  K                          ·                          Vcon                                                )                                            2                                                                      ·                Vcon                                      ]                                              (        A15        )                                          Id          ⁢                      xe2x80x83                    ⁢          2                =                                            1              2                        ⁡                          [                                                Ibs                  ⁢                                      xe2x80x83                                    ⁢                  1                                -                                                                                                    2                        ⁢                        Ibs                        ⁢                                                  xe2x80x83                                                ⁢                                                  1                          ·                          K                                                                    -                                                                        (                                                      K                            ·                            Vcon                                                    )                                                2                                                                              ·                  Vcon                                            ]                                .                                    (        A16        )            
FIG. 7 represents a relationship between Vcon, and Id1 and Id2. As shown in the figure, in a vicinity of Vcon=0, Id1 is directly proportional to Vcon and Id2 is directly proportional to xe2x88x92Vcon.
If                     A        =                              1            2                    ⁢          Ibs          ⁢                      xe2x80x83                    ⁢          1                                    (        A17        )                                B        =                              1            2                    ⁢                                                    2                ⁢                Ibs                ⁢                                  xe2x80x83                                ⁢                                  1                  ·                  K                                            -                                                (                                      K                    ·                    Vcon                                    )                                2                                                                        (        A18        )            
then from expressions A15-A18 currents Id1 and Id2 are represented by the following equations:
Id1=A+Bxc3x97Vcon xe2x80x83xe2x80x83(A19) 
Id2=Axe2x88x92Bxc3x97Vcon xe2x80x83xe2x80x83(A20). 
Current Id1 also flows through transistor M11. Since transistors M11 and M1 configure a current mirror circuit, current Id1 also flows through transistor M1. Therefore I1=Id1. Furthermore, current Id2 also flows through transistor M12. Since transistors M12 and M2 configure a current mirror circuit, current Id2 also flows through transistor M2. Therefore I2=Id2.                     C        =                              B            A                    =                                                                      2                  ⁢                  Ibs                  ⁢                                      xe2x80x83                                    ⁢                                      1                    ·                    K                                                  -                                                      (                                          K                      ·                      Vcon                                        )                                    2                                                                    Ibs              ⁢                              xe2x80x83                            ⁢              1                                                          (        A21        )            
is provided and from expressions A6 and A19-A21 gain is represented by the following equation:                               gain          ∝                                    (                                                I                  ⁢                                      xe2x80x83                                    ⁢                  1                                                  I                  ⁢                                      xe2x80x83                                    ⁢                  2                                            )                        0.5                          =                                            (                                                Id                  ⁢                                      xe2x80x83                                    ⁢                  1                                                  Id                  ⁢                                      xe2x80x83                                    ⁢                  2                                            )                        0.5                    ⁢                      
                    ⁢                      xe2x80x83                    =                                                    (                                                      A                    +                                          B                      ·                      Vcon                                                                            A                    -                                          B                      ·                      Vcon                                                                      )                            0.5                        ⁢                          
                        ⁢                          xe2x80x83                        =                                                            (                                                            1                      +                                              C                        ·                        Vcon                                                                                    1                      -                                              C                        ·                        Vcon                                                                              )                                0.5                            .                                                          (        A22        )            
In general, an exponential function is approximated by the following expression:
exp(2nx)≈{(1+x)/(1xe2x88x92x)}n xe2x80x83xe2x80x83(A23). 
If
Vconxe2x80x2=Cxc3x97Vcon xe2x80x83xe2x80x83(A24) 
and approximation A23 for n=0.5 is applied to expression A22, then
gain xe2x88x9d exp(Vconxe2x80x2) xe2x80x83xe2x80x83(A25). 
This indicates that the gain is proportional to an exponential function of a control voltage. If the gain is represented in dB then it exhibits a linear in dB characteristic relative the control voltage. A variable gain amplifier allowing a gain to have a linear in dB characteristic relative to a control voltage is referred to as a linear gain amplifier.
Approximation A23 for n=0.5, however, is established only in a small range. More specifically, for Y1={(1+x)/(1xe2x88x92x)}0.5 and Y2=exp(x), Y1 that allows an approximation Y1≈Y2 to be established has a small range. In other words, for the above described, conventional variable gain amplifier, a gain exhibits a linear in dB characteristic relative to a control voltage in a small range.
The present invention contemplates a variable gain amplifier allowing a gain to exhibit a linear in dB characteristic relative to a control voltage over a range wider than conventional.
The present invention in one aspect provides a variable gain amplifier including: an amplification circuit including first and second MOS transistors identical in characteristics and having respective sources connected to a first fixed potential, the amplification circuit having a differential gain proportional to a square root of a ratio between a current flowing through the first MOS transistor and a current flowing through the second MOS transistor; and a control circuit applying a potential corresponding to a constant voltage plus a control voltage to a gate of the first MOS transistor and a potential corresponding to the constant voltage minus the control voltage to a gate of the second MOS transistor.
As such, when the constant voltage and the control voltage are represented as Vb and Vcon, respectively, the first MOS transistor has its gate receiving a potential Vb+Vcon and the second MOS transistor has its gate-receiving a potential Vbxe2x88x92Vcon. As such, the first MOS transistor passes current I1 represented in the order of (Vb+Vcon)2 and the second MOS transistor passes current I2 represented in the order of (Vbxe2x88x92Vcon)2 so that a gain can exhibit A linear in dB characteristic for the control voltage over a range wider than conventional.